PARTNO    Applix_1617_SPAL1_V24;
                NAME      Applix_1617_SPAL1_V24;
                DATE      2023-10-27;
                REV       01 ;
                DESIGNER   ;

/*
2023-10-29 First draft guess at what is going on, 
	from looking at the circuit and the manual.
	Not tested yet!!!
*/

device g16V8;	/* modern replacement for 16L8 */

pin 1 = /A32_to_16_high;	/* from IC26 pin 8 */
pin 2 = /A15_to_A8_high;        /* from IC25 pin 8 */
pin 3 = a7;             /* from CPU */
pin 4 = a6;             /* from CPU */
pin 5 = a3;             /* from CPU */
pin 6 = a2;    	        /* from CPU */
pin 7 = a1;             /* from CPU */
pin 8 = rd_not_wr;      /* from CPU */
pin 9 = !LDS;           /* from CPU */



pin 19 = SD7;           /* to CPU */ 

pin 18 = DTACK;	        /* to CPU */ 

pin 17 = /SRWDAT;       /* to IC29 pin 11 (data latch) and IC7b pin 11 (SCOMMAND bits) */ 

pin 16 = STX_RDY        /* from IC17a pin 6 */

pin 15 = SRX_RDY        /* from IC18b pin 9 */

pin 14 = /SRDDAT;       /* to IC28 pin 1 (data latch /OE) and IC18b pin 13 (ZTXRDY bit) */

pin 13 = /SINT2;        /* to IC14 pin 11 */

pin 12 = /SCLRINT;      /* to IC14 pin 4 */

pin 11 = ZCMD;		/* from  IC18a pin 5 */


/*
$FFFFFC1 R/W    ZDATA    Read:  Data from Z80. 
​                         Write: Data to Z80.
$FFFFFC3 Read   SCLRINT  Clear 1616 interrupt.
$FFFFFC3 Write  SINTZ    Interrupt Z80.
$FFFFFC9 Read   SRXRDY   Bit 7 set if receive latch full.
$FFFFFCB Read   STXRDY   Bit 7 set if contents of the receive latch
​                         is a command.   
​$FFFFFD1 Write  SCOMMAND Write data to the data latch,
​                         set SCOMMAND bit.
*/

/*
Board responds at $FFFFFCx and FFFFFDx.

Intermediate terms:

*/

board    = A32_to_16_high & A15_to_A8_high & A7 & A6 & LDS ;

reg_1	= /A3 & /A2 & /A1
reg_3	= /A3 & /A2 &  A1
reg_9	=  A3 & /A2 & /A1
reg_b	=  A3 & /A2 &  A1
reg_9_or_b = A3 & /A2

read	=  rd_not_wr
write	= /rd_not_wr


/* Pins */

SRDDAT   = board & reg_1 & read ; 
 
SRWDAT   = board & reg_1 & write ;

SCLRINT  = board & reg_3 & read; 

SINTZ    = board & reg_3 & write;

DTACK.d  = 0;

SD7.d    = SRXRDY & reg_9 & read;
	 # STXRDY & reg_b & read;

/* Output enables */

DTACK.oe = board;
SD7.oe   = board & reg_9_or_b ;